The present invention relates mainly to a semiconductor memory circuit which needs a refresh operation, and to a technology effective for application to a pseudo static RAM or the like usable equally to a static RAM. (Random Access Memory) equivalently.
A so-called DRAM of a time multiplex system wherein in order to make it possible to cope with a DRAM in a manner similar to an SRAM (Static Random Access Memory), a read/write operation and a refresh operation are executed during one cycle with their times being allocated therefor, or the two operations are performed only when the read/write operation and the refresh operation compete with each other, has been proposed in Unexamined Patent Publication No. Sho 61 (1986)-71494.